I. Field of the Disclosure
The technology of the disclosure relates generally to memory data scrubbing in processor-based memory to provide data error correction to memory words stored in the memory.
II. Background
Magnetic random access memory (MRAM) is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) as part of an MRAM bitcell. In this regard, an exemplary MTJ 100 that can be provided in an MRAM bitcell is illustrated in FIG. 1. Data is stored in the MTJ 100 according to the magnetic orientation between two layers: a free ferromagnetic layer 102 (“free layer 102”) disposed above a fixed or pinned ferromagnetic layer 104 (“pinned layer 104”). The free and pinned layers 102, 104 are separated by a tunnel junction or barrier 106 formed by a thin non-magnetic dielectric layer. When the magnetic orientations of the free and pinned layers 102, 104 are anti-parallel (AP) to each other (shown in FIG. 1 as MTJ 100′), a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the free and pinned layers 102, 104 are parallel (P) to each other (shown in FIG. 1 as MTJ 100″), a second memory state exists (e.g., a logical ‘0’). The magnetic orientations of the free and pinned layers 102, 104 can be sensed to read data stored in the MTJ 100 by sensing the resistance when current flows through the MTJ 100. Data can also be written and stored in the MTJ 100 by applying a magnetic field to change the orientation of the free layer 102 to either a P or AP magnetic orientation with respect to the pinned layer 104.
One advantage of an MRAM is that MTJs in MRAM bitcells can retain stored information even when power is turned off. This is because data is stored in an MTJ as a small magnetic element rather than an electric charge or current. For example, in the MTJ 100 in FIG. 1, the free and pinned layers 102, 104 can store information even when the magnetic H-field is ‘0’ due to a hysteresis loop 108 of the MTJ 100.
One disadvantage of MRAM is data retention failure. The switching success ratio of a MTJ is not one hundred percent (100%) due to the probabilistic switching nature of the free layer in an MTJ. Further, as the integration density of computer memory chips increase, thus decreasing the size of individual memory cell structures, MRAM bitcells in an MRAM become more vulnerable to soft errors. Soft errors in MRAM bitcells are bit flip errors that can be caused by thermal stability issues in an MTJ. While the probability of a soft error occurring in an individual MRAM bitcell is low, the probability of soft errors occurring in an MRAM can still be significant, because a large amount of memory is typically provided in computer systems. Further, computer systems employing MRAM have months of uptime, which increases the possibility of soft errors occurring between power cycles and/or resets.
Data error correction systems, such as error-correcting code (ECC) systems, can be employed in MRAM systems to detect and correct bit errors that occur, including soft errors and the probabilistic switching nature of MTJs in an MRAM. In an ECC system, an ECC is calculated and stored in an ECC memory for each memory word written to memory. When a memory word is read from a memory location, an ECC is calculated on the stored memory word to determine if the ECC matches the ECC previously stored for a memory location when the memory word was written. If the ECCs match, the memory word is determined to not contain an error. If the ECCs don't match, the missing or erroneous bits in the memory word stored at the memory location are determined and fixed in the memory word provided for the read operation.
An ECC system can be provided as part of a memory data scrubbing process for an MRAM system. In a memory data scrubbing process, a memory controller in the MRAM system systematically scans through memory locations in the MRAM, detects bit errors at the scanned memory locations, and writes back corrected data to scanned memory locations that have bit errors. However, central processing unit (CPU) performance is decreased as a result of performing memory data scrubbing operations during regular CPU operation. To avoid such decrease in CPU performance, memory data scrubbing can be performed by a memory controller during CPU idle periods. The memory controller is powered up to provide memory data scrubbing during the CPU idle periods. However, additional power is still consumed in an undesirable manner by the memory controller when powering up to provide memory data scrubbing.